Last updated on January 21st, 2016 at 12:37 am
Singe Rank Memory can be memory with chips on only one side of the stick of memory, however Single Rank Memory can also have chips on both sides of the Stick as well. Single Rank Memory is distinguished by the information that is displayed on the information sticker on the memory, Single Rank has a 1Rx on it, for example 1Rx4 or 1Rx8, on the flip side Dual Rank Memory has a 2Rx on it, for example 2Rx4 or 2Rx8. (See Below for Examples)
Generally Single Rank Memory is faster than Dual Rank Memory, in laymen’s terms when a computer accesses Single Rank Memory it only has to go around the track once, where are Dual Rank it would have to go around the track twice.
For the most part Dual Rank Memory can be used in conjunction with Single Rank Memory, and in some cases when using a large amount of memory such as 16GB, servers motherboards actually require you to use a mix of Single and Dual Rank Memory.
The number of ranks on any DIMM is the number of independent sets of DRAMs that can be accessed for the full data bit‐width of the DIMM ie 64 bits. The ranks cannot be accessed simultaneously as they share the same datapath. The physical layout of the DRAM chips on the DIMM itself does not necessarily relate to the number of ranks. Sometimes the layout of all DRAM on one side of the DIMM PCB versus both sides is referred to as “single‐sided” versus “double‐sided”. These terms may cause confusion as they do not necessarily relate to how the DIMMs are logically organized or accessed.
For example, on a single rank DIMM that has 64 data bits of I/O pins, there is only one set of DRAMs that are turned on to drive a read or receive a write on all 64‐bits. In most electronic systems, memory controllers are designed to access the full data bus width of the memory module at the same time.
On a64‐bit (non‐ECC) DIMM made with two ranks, there would be two sets of DRAM that could be accessed at different times. Only one of the ranks can be accessed at a time, since the DRAM data bits are tied together for two loads on the DIMM (Wired OR). Ranks are accessed through chip selects (CS). Thus for a two rank module, the two DRAMs with data bits tied together may be accessed by a CS per DRAM (e.g. CS0 goes to one DRAM chip and CS1 goes to the other). DIMMs are currently being commonly manufactured with up to four ranks per module.
Consumer DIMM vendors have recently begun to distinguish between single and dual ranked DIMMs. JEDECdecided that the terms “dual‐sided,” “double‐sided,” or “dual‐banked” were not correct when applied to registered DIMMs. (from Wikipedia)
Information retrieved form MoyNetworks knowledgebase